High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices by stacking laminated semiconductor chips vertically stacked and interconnecting the semiconductor chips using through-silicon vias (TSVs) have been introduced. The TSVs are through electrodes that penetrate a semiconductor chip including a semiconductor substrate typically composed of silicon. Benefits of the 3D memory devices include a plurality of chips stacked with a large number of vertical vias between the plurality of chips and the memory controller, which allow wide bandwidth buses with high transfer rates between functional blocks in the plurality of chips and a considerably smaller footprint. Thus, the 3D memory devices contribute to large memory capacity, higher memory access speed and chip size reduction. The 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
Vias on the 3D memory devices may be formed by a “via middle” process. For example, the process may proceed by 1) disposing front bumps on a front surface of a semiconductor device; 2) thinning a back surface of a silicon substrate and exposing copper through-silicon vias by “Si reveal etching” during wafer processing (e.g., between transistor formation and a wiring process); 3) depositing a dielectric film, and 4) polishing the dielectric film by chemical mechanical planarization (CMP) to form back bumps. The via middle process described above, especially exposing copper through-silicon vias and polishing the dielectric film by CMP may cause significant manufacturing costs. In the manufacturing process, irregularity of back surface processing due to warpage of a wafer, heights of the copper through-silicon vias vary due to Si reveal etching, failures in exposing the copper through-silicon vias when a process window of the CMP is reduced, and scratches, cracks, etc., formed on a silicon board when the process window of the CMP is increased.